Ibm RS/6000 User Manual download pdf (Page 41)

The cache controller supports disable, inhibit and invalidate functions in addition to

the expected L2 memory caching operations.

2.2.3 The Memory Controller and PCI Bridge

The Memory Controller chip is directly attached to the processor bus and acts as a

PCI Bridge to the primary PCI bus as well.

It issues two different bus interfaces:

 The CPU bus interface that runs at 66 MHz

 The PCI bus interface that runs at 33 MHz

The memory controller supports address and data-bus parity generation and

checking. It provides support for Big- and Little-Endian modes and for 604 the

MESI protocol which is used as cache synchronization logic in SMP systems.

The PCI Bridge provides a low-latency path through which the processor may

directly access PCI devices mapped anywhere in the memory or I/O address

spaces. It also provides a high-bandwidth path giving the PCI bus Masters direct

access to main memory.

2.2.4 The System Memory

The PCI-based RS/6000 servers use JEDEC-Standard 168 pin, 5 volt, 70 nSec,

single bank, eight-byte parity or ECC memory DIMMs (Dual Inline Memory

Modules). By using DIMMs, you get the benefit of a 64-bit wide memory without

having to use paired or quad memory modules. In this way, you can upgrade

system memory using one DIMM module at a time, while maintaining maximum

flexibility and simplicity.

Either parity or ECC (Error Checking and Correcting) DIMMs may be used to

provide maximum flexibility. Even if parity DIMMs are used, the system implements

an ECC memory subsystem.

The Error Checking and Correcting (ECC) feature supported by the system memory

subsystem is a fault-tolerant one. ECC corrects single-bit memory failures that can

be induced temporarily by environment noises or permanently by hardware

problems. Using ECC will prevent the majority of memory failures from impacting

the system operation. ECC also provides double-bit memory error detection which

protects data integrity in the rare event of a double-bit failure.

The memory subsystem provides eight DIMM sockets for memory expansion that

are placed on the I/O Motherboard.

2.2.5 The Primary PCI Bus

The primary PCI bus is generated by the Memory Controller/Host Bridge chip. This

32-bit PCI bus is fully PCI 2.0 Specification compatible. It drives expansion card

slots as well as the secondary PCI bus bridge and the EISA bus bridge. In

addition, the MPIC (Multi-Processor Interrupt Controller) resides on the primary PCI

bus, as shown on Figure 5 on page 12.

Chapter 2. PCI-Based RS/6000 Server Hardware 17

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Ibm RS/6000 User Manual Page 41